Navitas Adds Top-Side Cooled QDPAK and Low-Profile TO-247-4L to its Package Line-Up in the Latest 5th Generation GeneSiC Technology

By Navitas Semiconductor Corporation | March 11, 2026, 8:30 AM

QDPAK and Low-profile TO247 in the latest GeneSiC™ 5th Generation Trench-Assisted Planar SiC MOSFET technology deliver significant improvements in performance and lifetime for AI data centers, grid and energy infrastructure, and industrial electrification with voltage ratings of 1200 V

Navitas Adds Top-Side Cooled QDPAK and Low-Profile TO-247-4L to its Package Line-Up in the Latest 5th Generation GeneSiC™ Technology

QDPAK and Low-profile TO247 in the latest GeneSiC™ 5th Generation Trench-Assisted Planar SiC MOSFET technology deliver significant improvements in performance and lifetime for AI data centers, grid and energy infrastructure, and industrial electrification with voltage
QDPAK and Low-profile TO247 in the latest GeneSiC™ 5th Generation Trench-Assisted Planar SiC MOSFET technology deliver significant improvements in performance and lifetime for AI data centers, grid and energy infrastructure, and industrial electrification with voltage

TORRANCE, Calif., March 11, 2026 (GLOBE NEWSWIRE) -- Navitas Semiconductor (Nasdaq: NVTS), an industry leader in next-generation GaNFast™ gallium nitride (GaN) and GeneSiC™ silicon carbide (SiC) power semiconductors, today announced the launch of two new packages: top-side cooled QDPAK and a low-profile TO-247-4L with asymmetrical leads in its 5th generation GeneSiC™ technology platform. The latest 1200 V SiC MOSFET products set a new industry benchmark for power density and ruggedness.

5th generation Trench-Assisted Planar (TAP) technology
This technology delivers 35% improvements in RDS,ON × QGD figure of merit (FoM), and about 25% improvement in QGD / QGS ratio. When coupled with stable high threshold voltage, VGS,TH, of >3 V, this technology ensures immunity against parasitic turn-on, providing a robust and predictable switching performance.

Top-side cooled (TSC) QDPAK
The QDPAK package is designed to overcome the thermal limitations of conventional PCB cooling by enabling heat dissipation directly through the top of the package to the heatsink. This optimized thermal path significantly improves heat dissipation efficiency and enables smaller system footprints. The package also minimizes parasitic inductance, supporting cleaner switching and higher efficiency at high frequencies. In addition, the QDPAK platform supports larger die sizes and higher current capability, facilitating the ultra-low RDS(ON) values for high-power applications, while its compact surface-mount profile enables scalable high-volume automated assembly.

  • Compact footprint: Features a 15 mm x 21 mm area with an ultra-low height of only 2.3 mm.
  • Enhanced creepage: Optimized with a groove in the package mold compound that extends creepage to 5 mm without trading off the area of the exposed top-side thermal pad.
  • High-voltage integration: Supports up to 1000 VRMS applications with an epoxy molding compound (EMC) featuring a Comparative Tracking Index (CTI) of >600.
  • Thermal integration: Designed for easier system-level thermal integration via top-side cooling.

Low-profile TO-247-4-LP
The low-profile TO-247-4-LP through-hole package variant is an optimized package for power electronics systems where vertical clearance is limited, such as high-density AI power racks. By minimizing the height of the package on the PCBA, this package enables higher power density when compared with systems made with a standard TO-247-4 package.

  • Density optimized: Provides a reduced vertical footprint on the PCBA to support compact form-factor requirements where conventional TO-247-4 package height is a constraint.
  • Manufacturing precision: Optimized with asymmetrical leads (thin leads for gate and Kelvin-source) to improve PCBA manufacturing tolerances.
  • AI Data Center ready: Specifically targeted at applications like AI data center power supplies, where form-factor and maximum allowable height are critical.

“Our customers are pushing the boundaries of what is possible in AI data center and energy infrastructure applications," said Paul Wheeler, VP & GM of the SiC business unit at Navitas. "The introduction of top-side cooled QDPAK, and low-profile TO-247-4-LP packages is a direct response to the need for 'more power in less space'”.

A white paper on the Trench-Assisted Planar technology is available for free download from the Navitas website.

Part NumberPackageVDS (V)RDS,ON (mΩ)
G5R06MT12QPQDPAK12006.5
G5R12MT12QPQDPAK120012
G5R06MT12LKTO-247-4-LP12006.5
G5R12MT12LKTO-247-4-LP120012


For further information, please visit –

To request samples, please contact a Navitas representative or write to [email protected].

*Navitas uses the term ‘AEC-Plus’ to indicate parts exceeding AEC-Q101 and JEDEC standards for reliability testing based on Navitas test results.

About Navitas
Navitas Semiconductor (Nasdaq: NVTS) is a next-generation power semiconductor leader in gallium nitride (GaN) and IC integrated devices, and high-voltage silicon carbide (SiC) technology, driving innovation across AI data centers, energy and grid infrastructure, performance computing, and industrial electrification. With more than 30 years of combined expertise in wide bandgap technologies, GaNFast™ power ICs integrate GaN power, drive, control, sensing, and protection, delivering faster power delivery, higher system density, and greater efficiency. GeneSiC™ high-voltage SiC devices leverage patented trench-assisted planar technology to provide industry-leading voltage capability, efficiency, and reliability for medium-voltage grid and infrastructure applications. Navitas has over 300 patents issued or pending and is the world’s first semiconductor company to be CarbonNeutral®-certified.

Navitas Semiconductor, GaNFast, GaNSense, GaNSafe, GeneSiC, and the Navitas logo are trademarks or registered trademarks of Navitas Semiconductor Limited or affiliates. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners.

Cautionary Statement Regarding Forward-Looking Statements
This press release includes “forward-looking statements” within the meaning of Section 21E of the Securities Exchange Act of 1934, as amended. Forward-looking statements are attempts to predict or indicate future events or trends or similar statements that are not a reflection of historical fact. Forward-looking statements may be identified by the use of words such as “we expect,” or “are expected to be,” “estimate,” “plan,” “project,” “forecast,” “intend,” “anticipate,” “believe,” “seek,” or other similar expressions. Forward-looking statements are made based on estimates and forecasts of financial and performance metrics, projections of market opportunity and market share and current indications of customer interest, all of which are based on various assumptions, whether or not identified in this press release. All such statements are based on current expectations of the management of Navitas and are not predictions of actual future performance. Forward-looking statements are provided for illustrative purposes only and are not intended to serve as, and must not be relied on by any investor as, a guarantee, an assurance, a prediction or a definitive statement of fact or probability. Actual events and circumstances are difficult or impossible to predict and will differ from assumptions and expectations. Many actual events and circumstances that affect performance are beyond the control of Navitas, and forward-looking statements are subject to a number of uncertainties. Our business is subject to certain risks that could materially and adversely affect our business, financial condition, results of operations, or the value of our securities. . For Navitas, these and other risk factors are discussed in the Risk Factors section of our most recent annual report on Form 10-K, as updated in the Risk Factors section of our most recent quarterly report on Form 10-Q, and in other documents we file with the SEC. If any of these risks, as discussed in more detail in our SEC reports, materialize or if our assumptions underlying forward-looking statements prove to be incorrect, actual results could differ materially from the results implied by these forward-looking statements. Examples of some of these risk factors include:

  • Risks Related to High-Power Markets: We intend to focus on AI data centers, performance computing, energy and grid infrastructure, and industrial electrification, and de-emphasize mobile and consumer products. We may not successfully execute our strategic transition to these new markets and customer applications, which could adversely affect our business, results of operations, and financial condition. This strategic realignment entails significant operational, technical, and market risks. Our success in these markets depends on factors including our ability to (i) develop and scale semiconductor solutions that meet demanding power, efficiency, and performance requirements of our customers; (ii) compete against established incumbents with substantial R&D and manufacturing resources; (iii) anticipate rapidly evolving customer needs and technological standards in these high-power and high-performance segments; and (iv) secure design wins and long-term supply agreements in new and unfamiliar market segments.
  • Market Acceptance and Addressable Market Uncertainty: The demand for our products, and our customers’ products, in new or emerging markets is difficult to forecast, as customer preferences may not be fully known and can evolve rapidly. Further, demand for our products depends on the acceptance of underlying new and developing system architectures. For example, our predictions for the use of GaN- and SiC-based products in 800V AI data center power applications depend on assumptions regarding the acceptance and growth of 800V systems themselves.
  • Unpredictable Competitive Dynamics and Industry Conditions: To the extent our products reshape or create new market landscapes, the competitive environment may evolve in unexpected ways. For example, new competitors may emerge, or traditional competitors with established R&D and manufacturing resources, and long-standing customer relationships, may choose to offer competitive GaN or high-voltage SiC solutions. In addition, the semiconductor sector is known for cyclical volatility. This inherent unpredictability is amplified in new and emerging markets, where demand can swing sharply due to macroeconomic events, supply chain shocks, regulatory changes, or technology cycles.
  • Other Risk Factors: Other risk factors include Navitas’ ability to diversify its customer base and develop relationships in new markets or regions; the possibility that the expected growth of our business will not be realized, or will not be realized within expected time periods, due to the above factors as well as others; Navitas’ ability to scale its technology into new markets and applications; the effects of competition on Navitas’ business, including actions of competitors with an established presence and resources in markets we hope to penetrate or by competitors to take market share in the markets we are deprioritizing; the level of demand in our customers’ end markets and our customers’ ability to predict such demand, both generally and with respect to successive generations of products or technology; Navitas’ ability to attract, train and retain key qualified personnel; changes in government trade policies, including the imposition of tariffs and the regulation of cross-border investments, particularly involving the United States and China; other regulatory developments in the United States, China and other countries; the impact of events such as epidemics and pandemics in locations where our products are manufactured and sold; and Navitas’ ability to protect its intellectual property rights.

Contact Information
Navitas Semiconductor
Vipin Bothra, VP Solution Marketing and Partnerships
[email protected]

Investor Contacts
Leanne Sievers | Brett Perry
Shelton Group
[email protected]

A photo accompanying this announcement is available at https://www.globenewswire.com/NewsRoom/AttachmentNg/dee05536-da56-418b-9462-05df1fceb632


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