Cadence Design Systems, Inc.’s CDNS has maintained a long-standing partnership with Taiwan Semiconductor Manufacturing Company (“TSMC”), which continues to strengthen over time. A couple of years back, Cadence expanded its collaboration with both TSMC and Microsoft MSFT to accelerate the physical verification of giga-scale digital designs. This initiative, leveraging the Cadence Pegasus Physical Verification System and CloudBurst Platform in combination with TSMC technology and Microsoft Azure cloud, was designed to help customers reduce design schedules and lower compute costs. Microsoft capitalizes on AI business momentum and Copilot adoption alongside accelerating Azure cloud infrastructure expansion.
Last year, Cadence collaborated with TSMC to improve efficiency and performance in AI-driven advanced-node designs and 3D-ICs, addressing the growing demand for advanced silicon solutions capable of handling large datasets and complex computations. TSMC approved Cadence’s leading digital and custom design flows for its latest N3 and N2P process technologies
Building on this foundation, in April 2025, Cadence announced the expansion of its partnership with TSMC to accelerate time-to-silicon for advanced-node and 3D-IC technologies. This enhanced collaboration integrates certified design flows, silicon-proven IP and ongoing technical innovation across TSMC’s most advanced nodes, including N2P, N3 and N5.
Recently, Cadence unveiled major advancements in chip design automation and IP, underscoring the impact of its deep collaboration with TSMC. Together, the companies are driving innovation in AI and high-performance computing (HPC), enabling faster delivery of next-generation semiconductor solutions.
Together, Cadence and TSMC have made significant progress across key areas ranging from AI-driven electronic design automation (EDA) to 3D-ICs, IP and photonics, providing the critical design infrastructure needed for next-generation technologies. The companies have worked side by side to enhance design capabilities for TSMC’s most advanced process nodes, including N3, N2 and A16.
What Does the Recent Collaboration Offer?
The collaboration is expanding to the upcoming A14 process, with the first PDK set for release later this year. In parallel, Cadence has introduced new silicon-proven IP on TSMC’s N3P node, further broadening design options for advanced applications.
These advancements are fueled primarily by AI-driven design solutions that enhance power, performance and area (PPA) optimization. Cadence’s JedAI platform, Cerebrus Intelligent Chip Explorer and AI-driven productivity tools within Innovus are tightly integrated with TSMC’s N2 process, with features such as automated design rule check (DRC) violation fixing for faster design closure.
For 3D-IC, Cadence has introduced innovations in bump connection automation, multi-chiplet implementation and smart alignment marker insertion, all of which complement TSMC’s advanced 3DFabric technology. In addition, solutions like Clarity 3D Solver, Sigrity X Platform and Optimality Intelligent System Explorer bring AI-driven automation to 3Dblox-based SI/PI analysis and optimization, streamlining complex system-level workflows.
On the IP front, Cadence is delivering cutting-edge solutions on TSMC’s N3P technology, enabling the bandwidth and connectivity demanded by today’s AI and HPC workloads. Highlights include the industry’s first HBM4 IP at N3P, high-speed memory interfaces such as LPDDR6/5X at 14.4G, DDR5 12.8G MRDIMM Gen2 and leading connectivity solutions like PCIe 7.0 at 128GT/s, 224G SerDes and UCIe 32G IP. These advancements address critical bottlenecks such as the memory wall in AI compute systems while supporting emerging AI PC and chiplet ecosystems with scalable, energy-efficient designs.
To strengthen its IP business, the company announced the acquisition of Secure-IC, which will expand its IP portfolio, including interface, memory, AI and DSP solutions. In April 2025, Cadence signed a definitive agreement with Arm Holdings to acquire its Artisan foundation IP business. The buyout includes a suite of standard cell libraries, memory compilers and general-purpose I/Os, all finely tuned for advanced process nodes at leading global foundries. Cadence has expanded systems business through partnerships with leading companies like NVIDIA Corporation NVDA, GlobalFoundries and IBM.
Recently, Cadence announced a major expansion of its Cadence Reality Digital Twin Platform with the addition of a digital twin of NVIDIA DGX SuperPOD with DGX GB200 systems. This new model of NVIDIA’s advanced accelerated computing platform gives data center designers and operators the ability to seamlessly integrate one of the world’s leading AI accelerators into the development of next-generation AI factories.
However, the company faces stiff competition from other EDA companies like Synopsys SNPS, ANSYS and Siemens AG. In the current economic scenario, as customers are strengthening their supplier relationships and focusing on cost efficiencies, many have selected Synopsys as their primary EDA partner. The recently completed acquisition of ANSYS by Synopsys holds profound implications for the semiconductor landscape. Moreover, broader market volatility amid evolving tariff situation and high operating costs remain a concern.
Want the latest recommendations from Zacks Investment Research? Today, you can download 7 Best Stocks for the Next 30 Days. Click to get this free report
Microsoft Corporation (MSFT): Free Stock Analysis Report NVIDIA Corporation (NVDA): Free Stock Analysis Report Synopsys, Inc. (SNPS): Free Stock Analysis Report Cadence Design Systems, Inc. (CDNS): Free Stock Analysis ReportThis article originally published on Zacks Investment Research (zacks.com).
Zacks Investment Research
